1. Field of the Invention
The present invention generally relates to a phase-locked loop (PLL). More particular, the present invention relates to a phase-locked loop with a digital frequency synthesizer featuring very accurate long-term phase and jitter stability
2. Description of Related Arts
In modern display system, a high speed (20–300 MHz) and low phase-drift clock is provided by a phase-locked loop (PLL) to digitize the graphics RGB signals while only an imprecise, very low frequency reference signal HSYNC of about 30–100 KHz is supplied to the system. The conventional PLL utilizes a frequency synthesizer configured with a delta-sigma fractional divider in PLL feedback loop and operates on N, N+1 basis, and usually the PLL input is directly from crystal such as 14 MHz or 20 MHz. This results in jitter at much lower offset frequencies that requires larger area to suppress.